A semiconductor device having a junction field effect transistor (i.e., a J-FET) in a prior art is disclosed in, for example, Japanese Patent Application Publication No. 2000-312008. The device is shown in FIG. 17. As shown in FIG. 17, the device includes a substrate J4 composed of an N+ conductive type substrate J1, an N− conductive type drift layer J2 and a P+ conductive type first gate layer J3, which are laminated in this order. A trench J5 is formed in the substrate J4 to penetrate the P+ conductive type first gate layer J3. An N− conductive type channel layer J6 and a P+ conductive type second gate layer J7 are formed in the trench J5. An N+ conductive type source layer J8 is formed in such a manner that an ion implantation is performed on the surface of the N− conductive type channel layer J6. In this construction, the P+ conductive type first gate layer J3 and the P+ conductive type second gate layer J7 sandwich the N− conductive type channel layer J6 so that an applied voltage applied to the P+ conductive type first gate layer J3 and to the P+ conductive type second gate layer J7 is controlled. Thus, extension of a depletion layer extending from the P+ conductive type first gate layer J3 and form the P+ conductive type second gate layer J7 is controlled so that a current between a source and a drain can be controlled.
In the semiconductor device having the above constitution, the extension of the depletion layer extending from the P+ conductive type first gate layer J3 and from the P+ conductive type second gate layer J7 is defined by an impurity concentration in the P+ conductive type first gate layer J3 and the P+ conductive type second gate layer J7 and by the impurity concentration in the N− conductive type channel layer J6. Therefore, the impurity concentration in each layer J3, J6, J7 and the thickness of the N− conductive type channel layer J6 are optimized so that the semiconductor device can provide a normally off type device.
When the normally off type semiconductor device made of silicon carbide is designed, the following points become mainly problems for obtaining a low on-state resistance.
(1) The P+ conductive type first and second gate layers J3, J7 works as a control gate so that the applied voltage applied to the P+ conductive type first and second gate layers J3, J7 is limited by a built-in potential in a silicon carbide matrix. For example, in case of 4H-SiC, the built-in potential is about 2.9V. Therefore, when the semiconductor device is operated under a high temperature about 250° C., the maximum value of the applied voltage applied to the P+ conductive type first and second gate layers J3, J7 is limited about 2.5V.
(2) In the normally off type semiconductor device, it is required to deplete the N− conductive type channel layer J6 completely by the depletion layer extending from the P+ conductive type first and second gate layers J3, J7. Thus, the N− conductive type channel layer J6 is required to become a low impurity concentration. Therefore, the N− conductive type channel layer J6 becomes a high resistance. Accordingly, the semiconductor device becomes a high on-state resistance so that the maximum current flowing through the device is limited.
In view of the above points, it is impossible to avoid the problem of No. (1) since the semiconductor device is made of silicon carbide. Therefore, it is required to solve the problem of No. (2) so that the on-state resistance of the silicon carbide semiconductor device is reduced as low as possible.